Copper dual damascene interconnects have been used in the semiconductor industry for years. However, the reduction in semiconductor feature sizes, for example below 10 nm, has led to the use of other fill material such as cobalt, to achieve suitable device performance. The inventors have observed that in interconnects having various feature sizes, filling each of the varying features sizes with cobalt can result in poor electrical properties, such as higher line resistances.
Accordingly, the inventors have developed improved techniques for selectively filling different sized features formed on a substrate with cobalt and copper.